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preliminary data STV8130AD adjustable and +3.3 v dual voltage regulator with disable and reset functions ? this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. september 2003 1/12 features n input voltage range: 5 v to 18 v n output currents up to 750 ma n fixed precision output 1 voltage: 3.3 v 2% n adjustable output 2 voltage: 2.8 to 16 v n output 1 with reset function n output 2 with disable function by ttl input n short-circuit protection at both outputs n thermal protection n low dropout voltage description the stv8130a # and stv8130d # are monolithic dual positive voltage regulators designed to provide a fixed precision output voltage of 3.3 v and an adjustable voltage between 2.8 and 16 v for currents up to 750 ma. an internal reset circuit generates a reset pulse when the voltage of output 1 drops below the regulated voltage value. output 2 can be disabled via the ttl input. short-circuit and thermal protections are included. sip9 (plastic package) order code: stv8130a# dip16 (8 + 8) order code: stv8130d# 9 8 7 6 5 4 3 2 1 output1 output2 program reset ground disable delay capacitor input2 input1 tab is connected to ground 1 2 3 4 5 6 7 8 11 12 13 14 15 16 input1 input2 delay capacitor disable reset program output2 output1 ground ground ground ground ground ground ground ground 10 9
STV8130AD 2/12 table of contents chapter 1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 chapter 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 absolute maximum ratings ................................................................................................ 4 2.2 thermal data .............................................................................................................. ........ 4 2.3 electrical characteristics ................................................................................................. ..... 4 chapter 3 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 chapter 4 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 chapter 5 power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . .8 chapter 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 chapter 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3/12 STV8130AD general information 1 general information figure 1: stv8130a # block diagram figure 2: stv8130d # block diagram 1 regulator 1 2 8 regulator 2 6 9 reference 7 4 input1 input2 disable output1 output2 reset delay capacitor program ground 5 3 protection 1 regulator 1 2 7 regulator 2 5 8 reference 6 4 input1 input2 disable output1 output2 reset delay capacitor program ground 3 protection pins 9 to 16
electrical characteristics STV8130AD 4/12 2 electrical characteristics 2.1 absolute maximum ratings 2.2 thermal data 2.3 electrical characteristics t amb = 25 c, v in1 = 7 v, v in2 = 10 v, unless otherwise specified. symbol parameter value unit v in dc input voltage at pins input1 and input2 20 v v dis disable input voltage at pin disable 20 v v rst output voltage at pin reset 20 v i out1,2 output currents internally limited p t power dissipation internally limited t stg storage temperature -65 to +150 c t j junction temperature 0 to +150 c symbol parameter value unit r thjc thermal resistance (junction-to-case) stv8130a # stv8130d # 9 15 c/w r thja thermal resistance 1 (junction-to-ambient) 1. mounted on board. for more information, refer to section 5 . stv8130a # stv8130d # 50 56 c/w t j maximum recommended junction temperature 140 c t oper operating free air temperature range 0 to +70 c symbol parameter test conditions min. typ. max. unit v out1 output voltage i out1 = 10 ma 3.23 3.30 3.37 v v out2 output voltage i out2 = 10 ma 2.8 16.0 v v io1,2 dropout voltage i out1,2 = 750 ma 1.4 v v o1,2li line regulation 6v < v in1 < 12 v 12 v < v in2 < 18 v i out1,2 = 200 ma 50 100 mv v o1,2lo load regulation 5ma < i out1 < 600 ma 5ma < i out2 < 600 ma 100 200 mv
5/12 STV8130AD electrical characteristics i q quiescent current i out1 = 10 ma, output2 disabled 2ma v o1rst reset threshold voltage 1 k = v out1 , i out1 3 50 ma k - 0.4 k - 0.25 k - 0.1 v v rth reset threshold hysteresis see circuit description. 20 50 75 mv t rd reset pulse delay c e = 100 nf see circuit description. 25 ms v rl saturation voltage in reset condition i reset = 5 ma 0.4 v i rh leakage current in normal condition v reset = 10 v 10 a k out1, 2 output voltage thermal drift t j = 0 to + 125c 100 ppm/c i out1,2sc short circuit output current v in1 = 7 v, v in2 = 10 v v in1,2 = 16 v 2 1.6 1.0 a v dish disable voltage when pin disable is high (output2 active) 2 v v disl disable voltage when pin disable is low (output2 disabled) 0.8 v i dis disable bias current 0v < v dis < 7 v -100 2 a v ref reference voltage at program pin 2.44 v t jsd junction temperature for thermal shutdown 145 c 1. this reset signal is activated by a decrease of v out1 voltage which can be due to an overload of pin out1 or by a lack of input voltage (v in1 ). 2. the output short-circuit currents are tested one channel at time. during a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. a safe permanent short-circuit protection is only guaranteed for input voltages up to 16 v. symbol parameter test conditions min. typ. max. unit k 0 d v 0 10 6 d tv 0 ------------------------ =
circuit description STV8130AD 6/12 3 circuit description the stv8130a # and stv8130d # are dual-voltage regulators with reset and disable functions. the two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during ews testing. since the supply voltage of this voltage reference is connected to pin input1 (v in1 ), the second regulator will not work if pin input1 is not supplied. the adjustable voltage of pin output2 (v out2 ) is defined by output bridge resistors (r1, r2): the values of these resistors are calculated to obtain, with the targetted value for v out2 , the reference voltage (v ref = 2.44 v) on the median point connected to pin program. the output stages are designed using a darlington configuration with a typical dropout voltage of 1.2 v. the disable circuit will switch off pin output2 if a voltage less than 0.8 v is applied to pin disable . the reset circuit checks the voltage at pin output1. if this voltage drops below v out1 - 0.25 v (3.05 v typ.), the "a" comparator ( figure 3 ) rapidly discharges the external capacitor (ce) and the reset output immediately switches to low. this drop can be caused by a parasitic loading condition on pin output1 or by a too low value of v in (short powering off). when the voltage at pin output1 exceeds v out1 - 0.2 v (3.1 v typ.), the v ce voltage increases linearly to the reference voltage (v ref = 2.44 v) corresponding to a reset pulse delay (t rd ) as shown in figure 4 . afterwards, the reset output returns to high. to avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.84 v). figure 3: reset diagram figure 4: internal reset voltages t rd c e 2.44v 10 m a ---------------------------- - = output1 reg v ref - + 50 a + - ce v ref 0.6v b reset 10 a 3 v ref = 2.44 v reset k v rth v o1rst t rd t rd v out1 power on power off k = actual value of v out1
7/12 STV8130AD application diagrams 4 application diagrams figure 5: stv8130a # typical application figure 6: stv8130d # typical application 3 9 8 4 5 2 1 reset v in2 v out1 v in1 v out2 ce 0.1 f c1 c2 c3 c4 disable c1 to c4 = 10 f 7 r1 r2 stv8130a # v o2 v ref r 1 r 2 + r 1 -------------------- = 6 delay output1 output2 program ground input1 input2 capacitor r1 value (typ.) = 10 k w v ref = 2.44 v reset disable 3 8 7 4 2 1 reset v in2 v out1 v in1 v out2 ce 0.1 f c1 c2 c3 c4 disable c1 to c4 = 10 f 6 r1 r2 stv8130d # v o2 v ref r 1 r 2 + r 1 -------------------- = 5 delay output1 output2 program input1 input2 capacitor r1 value (typ.) = 10 k w v ref = 2.44 v reset disable pins 9 to 16 ground
power dissipation and layout indications STV8130AD 8/12 5 power dissipation and layout indications the power is mainly dissipated by the two device buffers. it can be calculated by the equation: p = (v in1 -v out1 ) x i out1 + (v in2 -v out2 ) x i out2 the following table lists the different r thja values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: l maximum ambient temperature = 70 c l maximum junction temperature = 140 c device heat sink r thja in c/w p max in w stv8130a # no 50 1.4 yes 20 3.5 stv8130d # no 56 to 40 1.25 to 1.75 yes 32 2.2 figure 7: thermal resistance (junction-to-ambient) of dip16 package without heat sink figure 8: metal plate mounted near the stv8130d # for heat sinking copper area (cm2) (35 m plus solder) board is face-down to optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. 60 rthja c/w 40 50 10 12 0 55 45 24 8 6 test board with on board square heat sink area. top view bottom view
9/12 STV8130AD package mechanical data 6 package mechanical data figure 9: 9-pin plastic single in line package dim. mm inches min. typ. max. min. typ. max. a 7.1 0.280 a1 2.7 3 0.106 0.118 b 24.8 0.976 b1 0.5 0.020 b3 0.85 1.6 0.033 0.063 c 3.3 0.130 c1 0.43 0.017 c2 1.32 0.052 d 21.2 0.835 d1 14.5 0.571 e2.54 0.100 e3 20.32 0.800 l 3.1 1.122 l1 3 0.116 l2 17.6 0.693 l3 0.25 0.010 m 3.2 0.126 n 1 0.039
package mechanical data STV8130AD 10/12 figure 10: 16-pin plastic dual in-line package, 300-mil width dim. mm inches min. typ. max. min. typ. max. a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.56 0.014 0.022 b2 1.52 1.78 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 18.67 19.18 19.69 0.735 0.755 0.775 e2.54 0.100 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150
11/12 STV8130AD revision history 7 revision history revision main changes date 1.8 general update; disable pin renamed disable (function remains unchanged). august 2001 1.9 thermal data updated. september 2001 2.0 addition of dip16 package. september 2001 2.1 thermal data updated. figure 1 and figure 2 updated. october 2001 2.2 order code changed from stv8130a and stv8130d to stv8130a# and stv8130d#. update of v o1rst values in chapter 2.3: electrical characteristics on page 4 . 31 january 2002
STV8130AD 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pr eviously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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